View AK4390EF_2516196.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[ak4390] ms1046-e-00 2009/01 - 1 - general description the ak4390 is a high performance ster eo dac capable of sampling up to 216khz including a 32-bit digital filter. the modulator uses akm's multi-bit archit ecture, delivering wide dynamic range while preserving linearity for improved thd+n perform ance. the ak4390 has fully different ial switched-cap filter outputs, removing the need for ac coupling capacitors and incr easing performance for systems with excessive clock jitter. the ak4390 accepts 192khz pcm data, ideal for a wide range of applications including dvd-audio, high end sound cards, di gital audio firewire and usb inte rface boxes, and digital mixers. features ? 128-times oversampling ? sampling rate: 30khz 216khz ? 32bit 8x digital filter ripple: 0.005db, attenuation: 100db low latency option: 7/fs ? high tolerance to clock jitter ? low distortion differential output ? digital de-emphasis fo r 32, 44.1, 48khz sampling ? soft mute ? digital attenuator (255 levels and 0.5db step) ? thd+n: ? 103db ? dr, s/n: 120db ? audio format: 24/32bit msb justifie d, 16/20/24/32bit lsb justified, i 2 s ? master clock: 30khz ~ 32khz: 1152fs 30khz ~ 54khz: 512fs or 768fs 30khz ~ 108khz: 256fs or 384fs 108khz ~ 216khz: 128fs or 192fs ? power supply: 5v 5% ? ttl level digital i/f ? package: 30pin vsop ak4390 ultra low latenc y 32-bit ? dac
[ak4390] ms1046-e-00 2009/01 - 2 - block diagram mclk sdata lrck csn/smute bick cclk/dem0 cdti/dem1 dzfr aoutln vss1 vddr pdn avdd vss3 dvdd cad0 cad1/dif0 psn dzfl/dif1 dif2 vss2 vddl aoutlp aoutrp aoutrn vrefhl vrefll vreflr vrefll vss4 pcm data interface 8x interpolator control register datt soft mute '6 modulator clock divider scf scf vref block diagram
[ak4390] ms1046-e-00 2009/01 - 3 - ordering guide AK4390EF 10 a +70 q c 30pin vsop (0.65mm pitch) akd4390 evaluation board for ak4390 pin layout 6 5 4 3 2 1 smute/csn tst1/cad0 dem1/cdti dem0/cclk dif0/cad1 dif1/dzfl 7 psn 8 lrck sdata bick pdn dvdd vss4 mclk avdd ak4390 top view 10 9 tst2/dzfr aoutrp aoutrn 11 vss1 12 vss3 aoutlp aoutln vss2 25 26 27 28 29 30 24 23 21 22 20 19 dif2 vddr 13 vrefhr 14 vddl vrefhl 18 17 vreflr 15 vrefll 16
[ak4390] ms1046-e-00 2009/01 - 4 - pin/function no. pin name i/o function smute i soft mute in parallel control mode when this pin goes to ?h?, soft mute cycle is initiated. when returning to ?l?, the output mute releases. 1 csn i chip select in serial control mode tst1 i test pin in parallel control mode (internal pull-down pin) 2 cad0 i chip address 0 in serial control mode (internal pull-down pin) dem0 i de-emphasis enable 0 in parallel control mode 3 cclk i control data clock in serial control mode dem1 i de-emphasis enable 1 in parallel control mode 4 cdti i control data input in serial control mode dif0 i digital input format 0 in pcm mode 5 cad1 i chip address 1 in serial control mode dif1 i digital input format 1 in pcm mode 6 dzfl o left channel zero input detect in serial control mode 7 dif2 i digital input format 2 in pcm mode 8 psn i parallel/serial select (internal pull-up pin) ?l?: serial control mode, ?h?: parallel control mode tst2 i test pin in parallel control mode. connect to gnd. 9 dzfr o rch zero input detect in serial control mode 10 aoutrp o right channel positive analog output 11 aoutrn o right channel negative analog output 12 vss1 - connected to vss2/3/4 ground 13 vddr - right channel analog power supply, 4.75~5.25v 14 vrefhr i right channel high level voltage reference input 15 vreflr i right channel low level voltage reference input 16 vrefll i left channel low level voltage reference input 17 vrefhl i left channel high level voltage reference input 18 vddl - left channel analog power supply, 4.75~5.25v 19 vss2 - ground (connected to vss1/3/4 ground) 20 aoutln o left channel negative analog output 21 aoutlp o left channel positive analog output 22 vss3 - ground (connected to vss1/2/4 ground) 23 avdd - analog power supply, 4.75 to 5.25v 24 mclk i master clock input 25 vss4 - connected to vss1/2/3 ground 26 dvdd - digital power supply, 4.75 5.25v 27 pdn i power-down mode when at ?l?, the ak4390 is in power-down mode and is held in reset. the ak4390 should always be reset upon power-up. 28 bick i audio serial data clock in pcm mode 29 sdata i audio serial data input in pcm mode 30 lrck i l/r clock in pcm mode note: all input pins except internal pull-up/down pins should not be left floating.
[ak4390] ms1046-e-00 2009/01 - 5 - handling of unused pin the following tables illustrate recommended states for open pins: (1) parallel control mode classification pin name setting aoutlp, aoutln leave open. analog aoutrp, aoutrn leave open. digital smute connect to vss4. (2) serial control mode classification pin name setting aoutlp, aoutln leave open. analog aoutrp, aoutrn leave open. dif2 connect to vss4. digital dzfl, dzfr leave open.
[ak4390] ms1046-e-00 2009/01 - 6 - absolute maximum ratings (vss1 = vss2 = vss3 = vss4 = 0v; note 1 ) parameter symbol min max units power supplies: analog analog digital avdd vddl/r dvdd ? 0.3 ? 0.3 ? 0.3 6.0 6.0 6.0 v v v input current, any pin except supplies iin - 10 ma digital input voltage vind ? 0.3 dvdd+0.3 v ambient temperature (power applied) ta ? 10 70 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. vss1/2/3/4 must be connected to the same analog ground plane. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guara nteed at these extremes. recommended operating conditions (vss1 = vss2 = vss3 = vss4 =0v; note 1 ) parameter symbol min typ max units power supplies: ( note 3 ) analog analog digital avdd vddl/r dvdd 4.75 4.75 4.75 5.0 5.0 5.0 5.25 5.25 5.25 v v v voltage reference ( note 4 ) ?h? voltage reference ?l? voltage reference vrefh-vrefl vrefhl/r vrefll/r vref avdd-0.5 vss3 3.0 - - - avdd - avdd v v v note 1. all voltages with respect to ground. note 3. the power up sequence be tween avdd and dvdd is not critical. note 4. analog output voltage scales with the voltage of (vrefh ? vrefl). aout (typ.@0db) = (aout+) ? (aout ? ) = 2.8vpp (vrefhl/r ? vrefll/r)/5. * akemd assumes no responsibility for the usage beyond the conditions in this data sheet.
[ak4390] ms1046-e-00 2009/01 - 7 - analog characteristics (ta=25 c; avdd=vddl/r=dvdd=5.0v; vss1 = vss2 = vss3 = vss4 =0v; vrefhl/r=avdd, vrefll/r= vss1=vss2=vss3; input data=24bit; r l 1k ; bick=64fs; input signal frequency = 1khz; sampling frequency = 44.1khz; measurement bandwidth = 20hz ~ 20khz; external circuit: figure 15 ; unless otherwise specified.) parameter min typ max units resolution 24 bits dynamic characteristics ( note 5 ) fs=44.1khz bw=20khz 0dbfs ? 60dbfs ? 103 ? 57 93 - db db fs=96khz bw=40khz 0dbfs ? 60dbfs ? 100 ? 54 - - db db thd+n fs=192khz bw=40khz bw=80khz 0dbfs ? 60dbfs ? 60dbfs ? 100 ? 54 ? 51 - - - db db db dynamic range ( ? 60dbfs with a-weighted) ( note 6 ) 114 120 db s/n (a-weighted) ( note 7 ) 114 120 db interchannel isolation (1khz) 110 120 db dc accuracy interchannel gain mismatch 0.15 0.3 db gain drift ( note 8 ) 20 - ppm/ c output voltage ( note 9 ) 2.65 2.8 2.95 vpp load capacitance 25 pf load resistance ( note 10 )1 k power supplies power supply current normal operation (pdn pin = ?h?) avdd, vddl/r dvdd (fs 96khz) dvdd (fs = 192khz) 60 43 46 90 - 70 ma ma ma power down (pdn pin = ?l?) ( note 11 ) avdd+dvdd 10 100 a note 5. measured by audio precision, system two. averaging mode. refer to the evaluation board manual. note 6. by figure 15 . external lpf circuit example 2.101db for 16-bit data and 118db for 20-bit data. note 7. by figure 15 . external lpf circuit example 2. s/n does not depend on input word length. note 8. the voltage on (vrefhl/r ? vrefll/r) is held +5v externally. note 9. full-scale voltage(0db). output voltage scales with the voltage of (vrefhl/r ? vrefll/r). aout (typ.@0db) = (aout+) ? (aout ? ) = 2.8vpp (vrefhl/r ? vrefll/r)/5. note 10. for ac-load. 1.5k for dc-load note 11. in the power-down mode. psn pin = dvdd, and all other digital input pins including clock pins (mclk, bick and lrck) are held vss4. note 12. psr is applied to avdd, dvdd with 1khz, 100mvpp. the vrefhl/r pin is held +5v.
[ak4390] ms1046-e-00 2009/01 - 8 - sharp roll-off filter characteristics (fs = 44.1khz) (ta=25 c; avdd=vddl/r=4.75 ~ 5.25v, dvdd=4.75 ~ 5.25v; norm al speed mode; dem=off; sd bit =?0?) parameter symbol min typ max units digital filter passband ( note 14 ) 0.01db ? 6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 13 ) sb 24.1 khz passband ripple pr 0.005 db stopband attenuation sa 100 db group delay ( note 14 ) gd - 36 - 1/fs digital filter + scf frequency response : 0 20.0khz - 0.2 - db sharp roll-off filter characteristics (fs = 96khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; double speed mode; dem=off; sd bit=?0?) parameter symbol min typ max units digital filter passband ( note 13 ) 0.01db ? 6.0db pb 0 - 48.0 43.5 - khz khz stopband ( note 13 ) sb 52.5 khz passband ripple pr 0.005 db stopband attenuation sa 95 db group delay ( note 14 ) gd - 36 - 1/fs digital filter + scf frequency response : 0 40.0khz - 0.3 - db sharp roll-off filter characteristics (fs = 192khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; quad speed mode; dem=off; sd bit=?0?) parameter symbol min typ max units digital filter passband ( note 13 ) 0.01db ? 6.0db pb 0 - 96.0 87.0 - khz khz stopband ( note 13 ) sb 105 khz passband ripple pr 0.005 db stopband attenuation sa 90 db group delay ( note 14 ) gd - 36 - 1/fs digital filter + scf frequency response : 0 80.0khz - +0/ ? 1 - db note 13. the passband and stopband frequencies s cale with fs. for example, pb=0.4535fs (@ 0.01db), sb=0.546fs. note 14. the calculating delay time which occurred by digital filtering. this tim e is from setting the 16/20/24bit data of both channels to input register to the output of analog signal.
[ak4390] ms1046-e-00 2009/01 - 9 - short delay filter characteristics (fs = 44.1khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; normal speed mode; dem=off; sd bit=?1?) parameter symbol min typ max units digital filter passband ( note 14 ) 0.01db ? 6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 13 ) sb 24.1 khz passband ripple pr 0.005 db stopband attenuation sa 100 db group delay ( note 14 ) gd - 7 - 1/fs digital filter + scf frequency response : 0 20.0khz - 0.2 - db short delay filter characteristics (fs = 96khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; double speed mode; dem=off; sd bit=?1?) parameter symbol min typ max units digital filter passband ( note 13 ) 0.01db ? 6.0db pb 0 - 48.0 43.5 - khz khz stopband ( note 13 ) sb 52.5 khz passband ripple pr 0.005 db stopband attenuation sa 95 db group delay ( note 14 ) gd - 7 - 1/fs digital filter + scf frequency response : 0 40.0khz - 0.3 - db short delay filter characteristics (fs = 192khz) (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v; quad speed mode; dem=off; sd bit=?1?) parameter symbol min typ max units digital filter passband ( note 13 ) 0.01db ? 6.0db pb 0 - 96.0 87.0 - khz khz stopband ( note 13 ) sb 105 khz passband ripple pr 0.005 db stopband attenuation sa 90 db group delay ( note 14 ) gd - 7 - 1/fs digital filter + scf frequency response : 0 80.0khz - +0/ ? 1 - db
[ak4390] ms1046-e-00 2009/01 - 10 - dc characteristics (ta=25 c; avdd=vddl/r=4.75 ~ 5.25v, dvdd=4.75 ~ 5.25v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 2.4 - - - - 0.8 v v high-level output voltage (iout = ? 100 a) low-level output voltage (iout = 100 a) voh vol dvdd ? 0.5 - - - - 0.5 v v input leakage current ( note 15 ) iin - - 10 a note 15. tst1/cad0 and psn pins have internal pull-up devices, nominally 100k . therefore, tst1/cad0 and psn pins are not included in this specification.
[ak4390] ms1046-e-00 2009/01 - 11 - switching characteristics (ta=25 c; avdd=vddl/r=4.75 5.25v, dvdd=4.75 5.25v) parameter symbol min typ max units master clock timing frequency duty cycle fclk dclk 7.7 40 41.472 60 mhz % lrck frequency ( note 16 ) normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 30 30 108 45 54 108 216 55 khz khz khz % pcm audio interface timing bick period normal speed mode double speed mode quad speed mode bick pulse width low bick pulse width high bick ? ? to lrck edge ( note 17 ) lrck edge to bick ? ? ( note 17 ) sdata hold time sdata setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fn 1/64fd 1/64fq 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn high time csn ? ? to cclk ? ? cclk ? ? to csn ? ? tcck tcckl tcckh tcds tcdh tcsw tcss tcsh 200 80 80 50 50 150 50 50 ns ns ns ns ns ns ns ns reset timing pdn pulse width ( note 18 ) tpd 150 ns note 16. when the frequency (1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs) is switched, the ak4390 should be reset by the pdn pin or rstn bit. note 17. bick rising edge must not occur at the same time as lrck edge. note 18. the ak4390 can be reset by bringing the pdn pin ?l? to ?h?.
[ak4390] ms1046-e-00 2009/01 - 12 - timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil clock timing tlrb lrck vih bick vil tsds vih sdata vil tsdh vih vil tblr audio interface timing (pcm mode)
[ak4390] ms1046-e-00 2009/01 - 13 - tcss csn vih cclk vil vih cdti vil vih vil c1 c0 r/w a4 tcckl tcckh tcds tcdh write command input timing csn vih cclk vil vih cdti vil vih vil d3 d2 d1 d0 tcsw tcsh write data input timing tpd pdn vil power down & reset timing
[ak4390] ms1046-e-00 2009/01 - 14 - operation overview system clock the external clocks, which are required to operate the ak4390, are mclk, bick and lrck. mclk should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. sampling speed and mclk frequency are detected automatica lly and then the initial master clock is set to the appropriate frequency ( table 1 ). when external clocks are changed, the ak4390 should be reset by the pdn pin or rstn bit. after exiting reset (pdn pin = ?l? o ?h?) at power-up etc., the ak4390 is in power-down mode until mclk is supplied. the ak4390 is automatically placed in power saving mode when mclk and lrck stop during normal operation mode, and the analog output is avdd/2 (typ). when mclk and lrck are input again, the ak4390 is powered up. after power-up, the ak4390 is in the power-down mode until mclk and lrck are input. the mclk frequency corresponding to each sampling speed should be provided ( table 2 ). mclk mode sampling rate 1152fs normal 30khz~32khz 512fs 768fs normal 30khz~54khz 256fs 384fs double 30khz~108khz 128fs 192fs quad 108khz~216khz table 1. sampling speed lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 32.0khz n/a n/a 8.1920 12.2880 16.3840 24.5760 36.8640 44.1khz n/a n/a 11.2896 16.9344 22.5792 33.8688 n/a 48.0khz n/a n/a 12.2880 18.4320 24.5760 36.8640 n/a 88.2khz n/a n/a 22.5792 33.8688 n/a n/a n/a 96.0khz n/a n/a 24.5760 36.8640 n/a n/a n/a 176.4khz 22.5792 33.8688 n/a n/a n/a n/a n/a 192.0khz 24.5760 36.8640 n/a n/a n/a n/a n/a table 2. system clock example (n/a: not available) mclk= 256fs/384fs supports sampling rate of 30khz~108khz ( table 3 ). but, when the sampling rate is 30khz~54khz, dr and s/n will degrade by a pproximately 3db as compared to when mclk= 512fs/768fs. mclk dr,s/n 256fs/384fs 117db 512fs/768fs 120db table 3. relationship between mclk frequency and dr, s/n (fs= 44.1khz)
[ak4390] ms1046-e-00 2009/01 - 15 - audio interface format data is shifted in via the sdata pin using the bick and lrck inputs. eight data formats are supported, selected by the dif2-0 pins (parallel control mode) or dif2 -0 bits (serial control mode) as shown in table 4 . in all formats the serial data is msb-first, 2's compliment format and is latched on the ri sing edge of bick. mode 2 can be used for 20-bit and 16-bit msb justified formats by zeroing the unused lsbs. mode dif2 dif1 dif0 input format bick figure 0 0 0 0 16bit lsb justified t 32fs figure 1 1 0 0 1 20bit lsb justified t 48fs figure 2 2 0 1 0 24bit msb justified t 48fs figure 3 (default) 3 0 1 1 24bit i 2 s compatible t 48fs figure 4 4 1 0 0 24bit lsb justified t 48fs figure 2 5 1 0 1 32bit lsb justified t 64fs figure 5 6 1 1 0 32bit msb justified t 64fs figure 5 7 1 1 1 32bit i 2 s compatible t 64fs figure 6 table 4. audio interface format sdat a bick lrck sdat a 15 14 6 5 4 bick 0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1 3210 1514 ( 32fs ) ( 64fs ) 014 1 15 16 17 31 0 1 14 15 16 17 31 0 1 15 14 0 15 14 0 mode 0 don?t care don?t care 15:msb, 0:lsb mode 0 15 14 6 5 4 3 2 1 0 lch data rch data figure 1. mode 0 timing sdat a lrck bick ( 64fs ) 09 1 10 11 12 31 0 1 9 10 11 12 31 0 1 19 0 19 0 mode 1 don?t care don?t care 19:msb, 0:lsb sdat a mode 4 23:msb, 0:lsb 20 19 0 20 19 0 don?t care don?t care 22 21 22 21 lch data rch data 8 23 23 8 figure 2. mode 1/4 timing
[ak4390] ms1046-e-00 2009/01 - 16 - lrck bick ( 64fs ) sdat a 022 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 224 23 30 22 1 0 don?t care 23 22 23 figure 3. mode 2 timing lrck bick ( 64fs ) sdat a 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 224 23 25 22 1 0 don?t care 23 23 figure 4. mode 3 timing lrck bick ( 64fs ) sdat a 0 22 1 2 24 31 0 1 31 0 1 32:msb, 0:lsb 31 1 0 32 lch data rch data 23 30 22 224 23 30 31 1 0 32 31 32 figure 5. mode 5/6 timing lrck bick ( 64fs) sdat a 0 3 1 2 31 01 0 1 31:msb, 0:lsb 30 1 0 don?t care 31 lch data rch data 30 32 3 231 30 32 30 1 0 don?t care 31 31 figure 6. mode 7 timing
[ak4390] ms1046-e-00 2009/01 - 17 - de-emphasis filter a digital de-emphasis filter is available for 32khz, 44.1khz or 48khz sampling rates (tc = 50/15s) and it is enabled or disabled with the dem1-0 pins or de m1-0 bits. for 256fs/384fs and 128fs/192fs, th e digital de-emphasis filter is always off. when in dsd mode, the dem1-0 bits are ignored. the current value is held even if pcm mode and dsd mode are switched. dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 5. de-emphasis control output volume control the ak4390 includes channel independent digital output volume control (att) with 256 levels at 0.5db steps including mute. the volume control is in front of the dac, and it can attenuate the input data from 0db to ?127db and mute. when changing output levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions.
[ak4390] ms1046-e-00 2009/01 - 18 - zero detection the ak4390 has a channel-independent zero detect function. when the input data for each channel is continuously zero for 8192 lrck cycles, the dzf pin of each channel goes to ?h ?. the dzf pin of each channel immediately returns to ?l? if the input data of either channel is not zero after going to ?h?. if the rstn bit is ?0?, the dzf pins for both channels go to ?h?. the dzf pins of both channels go to ?l? 4 ~ 5/fs after the rstn bit returns to ?1?. if the dzfm bit is set to ?1?, the dzf pins of both channels go to ?h? only when th e input data for both channels are continuously zero for 8192 lrck cycles. the zero detect function can be disabled by setting the dzfe bit. in this case, dzf pins of both channels are always ?l?. the dzfb bit can i nvert the polarity of the dzf pin. soft mute operation the soft mute operation is performed in the digital domain. when the smute pin changes to ?h? or the smute bit set to ?1?, the output signal is attenuated by f during att_data u att transition time from the current att level. when the smute pin is returned to ?l? or the smute bit is returned to ?0?, the mute is cancelled and the output attenuation gradually changes to the att level during att_data u att transition time. if the soft mute is cancelled before attenuating f after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. the soft mute is effective for changing the signal source without stopping the signal transmission. smute pin or smute bit a ttenuation dzf pin att_level - f a out 8192/fs gd gd (1) (2) (3) (4) (1) (2) notes: (1) att_data u att transition time ( table 9 ). for this example, the time is 1020lrck cycles (1020/fs) at att_data=255 in normal speed mode. (2) analog output corresponding to digital input has group delay (gd). (3) if the soft mute is cancelled before attenuating f after starting the operation, the attenuation is discontinued and returned to att level by the same cycle. (4) when the input data for each channel is continuously zero for 8192 lrck cycles, the dzf pin for each channel goes to ?h?. the dzf pin immediately returns to ?l? if the input data are not zero after going ?h?. figure 7. soft mute function system reset the ak4390 should be reset once by bringing the pdn pin = ?l? upon power-up. the analog section exits power-down mode by mclk input and then the digital section exits power-down mode after the internal counter counts mclk during 4/fs.
[ak4390] ms1046-e-00 2009/01 - 19 - power on/off timing the ak4390 is placed in the power-down mode by bringing th e pdn pin ?l? and the registers are initialized. the analog outputs are floating (hi-z). as some click noise occurs at the edge of the pdn pin signal, the analog output should be muted externally if the click noise influences system application. the dac can be reset by setting rstn b it to ?0?. in this case, the register s are not initialized and the corresponding analog outputs go to avdd/2 (typ). as some click noise occurs at the edge of rstn signal, the analog output should be muted externally if click noise av ersely affect system performance. pdn pin power reset normal operation clock in mclk,lrck,bick dac in (digital) dac out (analog) external mute mute on (6) dzfl/dzfr don?t care ?0?data gd (2) (4) (5) (7) gd (4) mute on ?0?data don?t care internal state (3) (3) (1) notes: (1) after avdd and dvdd are powered-up, the pdn pin should be ?l? for 150ns. (2) the analog output corresponding to digital input has group delay (gd). (3) analog outputs are floating (hi-z) in power-down mode. (4) click noise occurs at the edge of pdn signal. this noise is output even if ?0? data is input. (5) mute the analog output externally if click noise (3) adversely aff ect system performance the timing example is shown in this figure. (6) dzfl/r pins are ?l? in the power-down mode (pdn pin = ?l?). (dzfb bit = ?0?) figure 8. power-down/up sequence example
[ak4390] ms1046-e-00 2009/01 - 20 - reset function (1) reset by rstn bit = ?0? when the rstn bit = ?0?, the ak4390?s digital section is powered down, but the internal register values are not initialized. the analog outputs settle to avdd/2 (typ) a nd the dzf pins for both channels go to ?h?. figure 9 shows the example of reset by rstn bit. internal state rstn bit d igital block p d normal o peration gd gd ?0 ? d a t a d/a out (analog) d/a in (digital) (1) (3) dzf (3) (1) (2) normal operation 2/ fs(4 ) internal rstn bit 2~3/fs (5) 3~4/fs (5) (6) notes: (1) the analog output corresponding to digital input has group delay (gd). (2) analog outputs settle to avdd/2 (typ). (3) click noise occurs at the edges (? n p ?) of the internal timing of rstn bit. this noise is output even if ?0? data is input. (4) dzf pins go to ?h? when the rstn bit is set to ?0?, and return to ?l? at 2/fs after the rstn bit becomes ?1?. (5) there is a delay, 3 ~ 4/fs from rs tn bit ?0? to the internal rstn bit ?0?, and 2 ~ 3/fs from rstn bit ?1? to the internal rstn bit ?1?. (6) mute the analog output externally if click noise (3) adversely aff ect system performance figure 9. reset sequence example 1
[ak4390] ms1046-e-00 2009/01 - 21 - (2) reset by mclk or lrck stop the ak4390 is automatically placed in reset state when mclk or lrck is stopped during normal operation and the analog outputs are floating (hi-z). when mclk and lrck are input again, the ak4390 exits reset state and starts the operation. zero detect function is disable when mclk or lrck is stopped. normal o peration internal state digital circuit p ower-down normal operation gd gd d/a out (analog) d/a in (digital) clock in mclk , bick, lrck (2) (3) externa l mute (6) (5) (2) mclk, bick, lrck stop rstb pin power-down power-down (4) (4) (4) hi-z (6) (5) (1) avdd pin dvdd pin (6) notes: (1) after avdd and dvdd are powered-up, the pdn pin should be held ?l? for 150ns. (2) the analog output corresponding to digital input has the group delay (gd). (3) digital data can be stopped. the click noise after mclk and lrck are input again can be reduced by inputting the ?0? data during this period. (4) click noise occurs in 3 4lrck cycles ether on a rising edge ( ) of the pdn signal or mclk inputs. this noise is output even if ?0? data is input. (5) mute the analog output externally if click noise (4) influences system application. the timing example is shown in this figure. figure 10. reset sequence example 2
[ak4390] ms1046-e-00 2009/01 - 22 - register control interface pins (parallel control mode) or registers (serial control mode ) can control the functions of the ak4390. in parallel control mode, the register setting is ignored, and in serial control mode the pin settings ar e ignored. when the state of the psn pin is changed, the ak4390 should be reset by the pdn pin. the serial control interface is enabled by the psn pin = ?l?. in this mode, pin settings must be all ?l?. internal register s may be written to through3-wire p interface pins: csn, cclk and cdti. the data on this interface consis ts of chip address (2-bits, cad0/1), r ead/write (1-bit; fixed to ?1?), register address (msb first, 5-bits) and control data (msb first, 8- bits). the ak4390 latches the data on the rising edge of cclk, so data should be clocked in on the falling edge. the writing of data is valid when csn ? n ?. the clock speed of cclk is 5mhz (max). function parallel control mode serial control mode audio format y y de-emphasis y y smute y y dsd mode - y ex df i/f - y short delay filter - y digital attenuator - y table 6. function list (y: available, -: not available) setting the pdn pin to ?l? resets the registers to their default values. in serial control mode, the internal timing circuit is reset by the rstn bit, but the registers are not initialized. cdti cclk c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 csn c1-c0: chip address (c1=cad1, c0=cad0) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 11. control i/f timing * the ak4390 does not support the read command. * when the ak4390 is in power down mode (pdn pin = ?l?) or the mclk is not provided, writing into the control register is prohibited. * the control data can not be written when the cclk rising edge is 15 times or less or 17 times or more during csn is ?l?.
[ak4390] ms1046-e-00 2009/01 - 23 - function list function default address bit pcm dsd ex df i/f attenuation level 0db 03h 04h att7-0 y y y external digital filter i/f mode disable 00h exdf y - y ex df i/f mode clock setting 16fs(fs=44.1khz) 00h esc - - y audio data interface modes 24bit msb justified 00h dif2-0 y - - data zero detect enable disable 01h dzfe y y - data zero detect mode separated 01h dzfm y y short delay filter enable sharp roll-off filter 01h sd y - - de-emphasis response off 01h dem1-0 y - - soft mute enable normal operation 01h smute y y y dsd/pcm mode select pc m mode 02h dp y y - master clock frequency select at dsd mode 512fs 02h dcks - y - mono mode stereo mode sel ect stereo 02h mono y y y inverting enable of dzf ?h? active 02h dzfb y y - the data selection of l channel and r channel r channel 02h sellr y y y table 7. function list2 (y: available, -: not available)
[ak4390] ms1046-e-00 2009/01 - 24 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 0 0 dif2 dif1 dif0 rstn 01h control 2 dzfe dzfm sd dfs1 dfs0 dem1 dem0 smute 02h control 3 0 0 0 0 0 dzfb 0 0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 notes: data must not be written into addresses from 05h to 1fh. when the pdn pin goes to ?l?, the registers are initialized to their default values. when rstn bit is set to ?0?, only the internal timing is reset, and the registers are not initialized to their default values. when the state of the psn pin is changed, the ak4390 should be reset by the pdn pin. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 0 0 0 0 dif2 dif1 dif0 rstn default 0 0 0 0 0 1 0 1 rstn: internal timing reset 0: reset. all registers are not initialized. 1: normal operation (default) when internal clocks are changed, the ak4390 should be reset by the pdn pin or rstn bit. dif2-0: audio data interface modes ( table 4 ) initial value is ?010? (mode 2: 24-bit msb justified).
[ak4390] ms1046-e-00 2009/01 - 25 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 dzfe dzfm sd 0 0 dem1 dem0 smute default 0 0 0 0 0 0 1 0 smute: soft mute enable 0: normal operation (default) 1: dac outputs soft-muted. dem1-0: de-emphasis response ( table 5 ) initial value is ?01? (off). sd: short delay filter enable 0: sharp roll-off filter (default) 1: short delay filter dzfm: data zero detect mode 0: channel separated mode (default) 1: channel and?ed mode if the dzfm bit is set to ?1?, the dzf pins of both channels goes to ?h? only when the input data for both channels are continuously zero for 8192 lrck cycles. dzfe: data zero detect enable 0: disable (default) 1: enable the zero detect function can be disabled by dzfe bit ?0?. in this case, the dzf pins of both channels are always ?l?.
[ak4390] ms1046-e-00 2009/01 - 26 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 0 0 0 0 0 dzfb 0 0 default 0 0 0 0 0 0 0 0 dzfb: inverting enable of dzf 0: dzf pin goes ?h? at zero detection (default) 1: dzf pin goes ?l? at zero detection addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h lch att att7 att6 att5 att4 att3 att2 att1 att0 04h rch att att7 att6 att5 att4 att3 att2 att1 att0 default 1 1 1 1 1 1 1 1 att7-0: attenuation level 256 levels, 0.5db step data attenuation ffh 0db feh -0.5db fdh -1.0db : : : : 02h -126.5db 01h -127.0db 00h mute (- ) the transition between set values is a soft transiti on of 7425 levels. it takes 7424/fs (168ms@fs=44.1khz) from ffh (0db) to 00h (mute). if the pdn pin goes to ?l?, the atts are initialized to ffh. the att values are ffh when rstn = ?0?. when rstn retu rn to ?1?, the att values fade to their current value. this digital attenuator is independent of the soft mute function.
[ak4390] ms1046-e-00 2009/01 - 27 - system design figure 12 shows the system connection diagram. figure 14 and figure 15 shows the analog output circuit examples. the evaluation board (akd4390) demonstrates the optimum lay out, power supply arrangements and measurement results. 6 5 4 3 2 1 csn cad0 cdti cclk cad1 dzfl 7 psn 8 lrck sdata bick pdn dvdd vss4 mclk avdd ak4390 top view 10 9 dzfr aoutrp aoutrn 11 vss1 12 vss3 aoutlp aoutln vss2 25 26 27 28 29 30 24 23 21 22 20 19 dif2 vddr 13 vrefhr 14 vddl vrefhl 18 17 vreflr 15 vrefll 16 analog 5.0v ceramic ca p acitor + electrol y tic capacitor lch lpf lch mute micro- controller lch out 10u + rch lpf rch mute rch out a nalog ground digital ground dsp digital 5.0v + + + + + 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 10u 10u 10u 10u 10u notes: - power lines of avdd and dvdd should be distributed separa tely from the point with low impedance of regulator etc. - vss1/2/3/4 must be connected to the same analog ground plane. - when aout drives a capacitive load, some resistan ce should be added in series between aout and the capacitive load. - all input pins except pull-down/pull-up pins should not be allowed to float. figure 12. typical connec tion diagram (avdd=5v, dvdd=5v , serial control mode)
[ak4390] ms1046-e-00 2009/01 - 28 - analog ground digital ground system controller tst1/cad0 dem0/cclk 3 dem1/cdti 4 dif0/cad1 5 dif1/dzfl 6 dif2 7 psn 8 tst2/dzfr 9 aoutrp 10 aoutrn 11 vss1 12 vdrr 13 sdata 29 bick 28 pdn 27 dvdd 26 vss4 25 mclk 24 avdd 23 vss3 22 aoutlp 21 aoutln 20 vss2 19 vddl ak4390 18 14 15 17 16 vrefhr vreflr vrefhl vrefll smute/csn lrck 30 2 1 figure 13. ground layout 1. grounding and power supply decoupling to minimize coupling by digital noise, decoupling capacito rs should be connected to avdd and dvdd, respectively. avdd is supplied from analog supply in system and dvdd is supplied from digital supply in system. power lines of avdd and dvdd should be distributed separately from the point with low impedance of regulator etc. the power up sequence between avdd and dvdd is not critical. vss1/2/3/4 must be connected to the same analog ground plane. decoupling capacitors for high fre quency should be placed as near as possible to the supply pin. 2. voltage reference the differential voltage between vrefhl/r and vrefll/ r sets the analog output range. the vrefhl/r pin is normally connected to avdd, and the vrefll/r pin is normally connected to vss1/2/3. vrefhl/r and vrefll/r should be connected with a 0.1f ceramic capacitor. all si gnals, especially clocks, should be kept away from the vrefhl/r and vrefll/r pins in order to avoid unwanted noise coupling into the ak4390. 3. analog outputs the analog outputs are fully differential outputs at 2.8vpp (typ, vrefhl/r ? vrefll/r = 5v), centered around avdd/2 (typ). the differential out puts are summed externally, v aout = (aout+) ? (aout ? ) between aout+ and aout ? . if the summing gain is 1, the output range is 5.6vpp (typ, vrefhl/r ? vrefll/r = 5v). the bias voltage of the external summing circuit is supplied externally. the input data format is two?s complement. the output voltage (v aout ) is positive full scale for 7fffffh (@24-bits) and negative full scale for 800000h (@24-bits). the ideal v aout is 0v for 000000h(@24-bits). the internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulat or beyond the audio passband. figure 14 shows an example of an external lpf circuit summing the differential outputs with an op-amp. figure 15 shows an example of differential outputs and a lpf circuit example by three op-amps.
[ak4390] ms1046-e-00 2009/01 - 29 - 1.5k 1.5k 750 1.5k 750 1.5k 1n +vop 1n -vop aout- aout+ 2.2n analog out ak4390 figure 14. external lpf circuit example 1 for pcm (fc = 125khz, q=0.692) frequency response gain 20khz ? 0.012db 40khz ? 0.083db 80khz ? 0.799db table 8. filter response of external lpf circuit example 1 for pcm 330 100u 180 a outl- 10k 3.9 n 1.2k 680 3.3n 6 4 3 2 7 10u 0.1u 0.1u 10u 10u njm5534d 330 100u 180 a outl+ 10k 3.9n 1.2k 680 3.3n 6 4 3 2 7 10u 0.1u 0.1 u 10u njm5534d 0.1u + njm5534d 0.1u 10u 100 4 3 2 1.0n 620 620 560 7 + + + + - + - + + + - + + 1.0n lch -15 +15 6 560 figure 15. external lpf circuit example 2 for pcm 1 st stage 2 nd stage total cut-off frequency 182khz 284khz - q 0.637 - - gain +3.9db -0.88db +3.02db 20khz -0.025 -0.021 -0.046db 40khz -0.106 -0.085 -0.191db frequency response 80khz -0.517 -0.331 -0.848db table 9. filter response of external lpf circuit example 2 for pcm
[ak4390] ms1046-e-00 2009/01 - 30 - package detail a note: dimension "*" does not include mold flash. 0.22 0.1 0.65 *9.7 0.1 1.5max a 1 15 16 30 30pin vsop (unit: mm) 5.6 0.1 7.6 0.2 0.45 0.2 -0.05 +0.10 0.3 0.15 0.12 m 0.08 1.2 0.10 0.10 +0.10 -0.05 v material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder (pb free) plate
[ak4390] ms1046-e-00 2009/01 - 31 - marking AK4390EF xxxxxxxxx xxxxxxxxx date code identifier revision history date (yy/mm/dd) revision reason page contents 09/01/09 00 first edition
[ak4390] ms1046-e-00 2009/01 - 32 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei emd corporation (akemd) or authorized distributors as to current status of the products. z akemd assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akemd products are neither intended nor au thorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akemd assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akemd. as used here: note1) a critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fi elds, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akemd pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above cont ent and conditions, and the buyer or distributor agrees to assume any and all re sponsibility and liability for and hold akemd harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4390EF

	To Download AK4390EF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .